1. Field of the Invention
Embodiments of the invention relate generally to a voltage booster for a semiconductor device. More particularly, embodiments of the invention relate to a voltage booster and associated initial voltage boosting circuit adapted for use in a semiconductor device having a power-saving mode.
A claim of priority is made to Korean Patent Application No. 2006-0067040 filed on Jul. 18, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Modern semiconductor devices tend to operate using relatively low internal operating voltages. The relatively low internal operating voltages are typically generated by applying a relatively high external power supply voltage to the semiconductor devices and then stepping down the relatively high external power supply voltage. Initial application of an external power supply voltage to a semiconductor device and subsequent generation of internal operating voltage(s) is commonly referred to as a “power-up” operation of the semiconductor device. In the power-up operation, the semiconductor device will not typically begin to operate immediately after the external power supply voltage is initially applied to the semiconductor device. Instead, the semiconductor device typically first goes through a process of stabilization of the internal operating voltages. In general, this stabilization process is carried out using an initial voltage boosting circuit, which is a type of stabilization circuit.
In addition, certain types of semiconductor devices also use internal operating voltages that are higher than the external power supply voltage. For example, a boosting voltage Vpp higher than an external power supply voltage VDD may be used to access memory cells in a dynamic random access memory (DRAM). In the DRAM, circuits such as a word line driver circuit, a bit line isolation circuit, and a data output buffer circuit may use boosting voltage Vpp. Where semiconductor devices use a boosting voltage, the power-up operation generally further includes operations for boosting the external power supply voltage.
One reason why semiconductor devices may use internal operating voltages higher than the external power supply voltage is because the operation of some features in the device may require relatively high voltages compared with other features. For example, memory cell transistors in a DRAM may have higher threshold voltages than other transistors in the DRAM due to a relatively small size of the memory cell transistors. Accordingly, a word line driver circuit may apply the boosting voltage to word lines in the DRAM in order to access the memory cell transistors in the DRAM.
In general, the operation of a semiconductor device is unreliable until the internal operating voltages stabilize during some period of time after the external power supply voltage is applied to the semiconductor device. Accordingly, to monitor the stabilization of the internal operating voltages, the semiconductor device may generate a power-up signal /PWRUP indicating whether an internal power supply voltage has reached a predetermined internal power supply voltage target level. Once the internal operating voltages stabilize, control signals required for operation of the semiconductor device may be effectively controlled.
Where the internal power supply voltage has not yet reached the predetermined internal power supply voltage target level, power-up signal /PWRUP increases in response to the external power supply voltage. Then, once the internal power supply voltage reaches the predetermined internal power supply voltage target level, power-up signal /PWRUP transitions to a logic level “low”, indicating that the internal power supply voltage is above the predetermined internal power supply voltage target level and therefore the internal operating voltages of the semiconductor device have stabilized.
FIG. 1 is a circuit diagram of a conventional initial voltage boosting circuit for a semiconductor device. The initial voltage boosting circuit receives power-up signal /PWRUP and increases a voltage level apparent on a voltage boosting terminal VPP based on a logic level of power up signal /PWRUP.
Referring to FIG. 1, the initial voltage boosting circuit comprises a level shifter 10, an initial voltage booster 20, and a first inverter INV1. Level shifter 10 comprises first through fourth negative metal-oxide semiconductor (NMOS) transistors N1 through N4, first and second positive metal-oxide semiconductor (PMOS) transistors P1 and P2, and a second inverter INV2. Initial voltage booster 20 includes a third PMOS transistor P3.
In level shifter 10, first PMOS transistor P1 has a first terminal receiving boosting voltage Vpp, a second terminal, and a gate. Second PMOS transistor P2 has a first terminal receiving boosting voltage Vpp, a second terminal connected to the gate of first PMOS transistor P1, and a gate connected to the second terminal of first PMOS transistor P1. First NMOS transistor N1 has a first terminal connected to the second terminal of first PMOS transistor P1 through a first node No1, a second terminal, and a gate receiving external power supply voltage VDD. Second NMOS transistor N2 has a first terminal connected to the second terminal of first NMOS transistor N1, a second terminal connected to ground, and a gate. Third NMOS transistor N3 has a first terminal connected to the second terminal of second PMOS transistor P2 through a second node No2, a second terminal, and a gate receiving external power supply voltage VDD. Fourth NMOS transistor N4 has a first terminal connected to the second terminal of third NMOS transistor N3, a second terminal connected to ground, and a gate. Second inverter INV2 has an input terminal connected to the gate of second NMOS transistor N2 and an output terminal connected to the gate of fourth NMOS transistor N4. Second node No2 is connected to a level shifter output terminal LS_OUT.
First inverter INV1 has an input terminal receiving power-up signal /PWRUP, and an output terminal connected to the gate of second NMOS transistor N2. First inverter outputs an inverted power-up signal /PWRUP on its output terminal.
In initial voltage booster 20, third PMOS P3 transistor has a first terminal and a bulk receiving boosting voltage Vpp from a voltage boosting circuit (not shown), a second terminal connected to external power supply voltage VDD, and a gate connected to level shifter output terminal LS_OUT.
The operation of the initial voltage boosting circuit of FIG. 1 will now be described in further detail.
Since first and third NMOS transistors N1 and N3 both have gates connected to external power supply voltage VDD, first and third NMOS transistors N1 and N3 are turned on. Where power-up signal /PWRUP has a logic level “low”, second NMOS transistor N2 is turned on, and fourth NMOS transistor N4 is turned off. Thus, node No1 assumes ground voltage VSS and second PMOS transistor P2 is turned on. As a result, node No2 receives boosting voltage Vpp, turning off first PMOS transistor P1. Since node No2 receives boosting voltage Vpp, boosting voltage Vpp is output on level shifter output terminal LS_OUT.
Under these conditions, boosting voltage Vpp is applied to the gate of third PMOS transistor P3 in initial voltage booster 20, turning off third PMOS transistor P3. As a result, external power supply voltage VDD is not connected to voltage boosting terminal VPP and initial voltage booster 20 does not generate an initial boosting voltage Vp in response to a rise in external power supply voltage VDD. Instead, the voltage boosting circuit performs a charge pumping operation and generates boosting voltage Vpp at a predetermined target voltage level.
Where power-up signal /PWRUP has a logic level “high”, second NMOS transistor N2 is turned off and fourth NMOS transistor N4 is turned on. Accordingly, node No2 assumes ground voltage VSS and first PMOS transistor P1 is turned on. As a result, node No1 receives boosting voltage Vpp and second PMOS transistor P2 is turned off. Since node No2 is at voltage VSS, ground voltage VSS is output on level shifter output terminal LS_OUT
Under these conditions, ground voltage VSS is applied to the gate of PMOS transistor P3, turning on PMOS transistor P3. As a result, external power supply voltage VDD is connected to voltage boosting terminal VPP so that initial voltage booster 20 generates initial boosting voltage Vp in response to a rise in external power supply voltage VDD.
FIG. 2 is a voltage diagram illustrating an increase in boosting voltage Vpp over time and a charge pumping period in the initial voltage boosting circuit illustrated in FIG. 1. In FIG. 2, time is plotted on the x-axis and voltage is plotted on the y-axis. A text label “VEXT” denotes a waveform of external power supply voltage VDD applied to internal circuits of the semiconductor device of FIG. 1 during a normal power-on operation. A text label “VINT” denotes a waveform of an internal power supply voltage VINT applied to the internal circuits. A text label “/PWRUP” denotes a waveform of power-up signal /PWRUP used to indicate when internal power supply voltage VINT is above the predetermined internal power supply voltage target level. A text label “VPP” denotes a waveform of boosting voltage Vpp generated by performing a boosting operation and a pumping operation in response to power-up signal /PWRUP.
In FIG. 2, a first period is delimited by an initial time point when external power supply voltage VDD is first applied to internal circuits of the semiconductor device, and a first time point T1 when internal power supply voltage VINT reaches the predetermined internal power supply voltage target level. During the first period, external power supply voltage VDD increases from 0V, internal power supply voltage VINT increases in response to the increase of external power supply voltage VDD, and power-up signal /PWRUP increases along with the increase in internal power supply voltage VINT.
At time point T1, when internal power supply voltage VINT reaches the predetermined internal power supply voltage target level, power-up signal /PWRUP transitions to logic level “low” to enable a charge pumping operation. The charge pumping operation is performed after time point T1 to elevate the level of boosting voltage Vpp. Accordingly, a second period following time point T1 will be referred to as a “boosting voltage pumping operation period”.
As described above, boosting voltage Vpp with a voltage level higher than a voltage level of external power supply voltage VDD can be used as an internal operating voltage for a semiconductor device, e.g., for turning on memory cell transistors in a DRAM via word lines. In order to generate boosting voltage Vpp as illustrated in FIG. 2, boosting voltage Vpp is first increased by a boosting operation in the first period and then further increased by a charge pumping operation in the second period.
Some semiconductor devices use a power-saving mode to conserve power. For example, the power-saving mode can play an important role in semiconductor devices included in portable electronic devices since limited power (e.g., battery life) tends to play an important role in the utility of such portable devices. The power-saving mode is typically enabled in response to a power-saving mode enable signal.
In the power-saving mode, internal power supply voltage VINT is intentionally decreased to conserve power. As an example, in the power-saving mode, internal power supply voltage VINT and boosting voltage Vpp of FIG. 1 may decrease. In the example of FIG. 1, absent the power-saving mode, the amplitude of boosting voltage Vpp exceeds the amplitude of external power supply voltage VDD and the threshold voltage of various transistors in the semiconductor device. However, where boosting voltage Vpp decreases, the amplitude of boosting voltage Vpp may fall below the amplitude of external power supply voltage VDD and the threshold voltage of the transistors in the semiconductor device. More particularly, in the example of FIG. 1, the amplitude of boosting voltage Vpp may fall below the threshold voltage of third PMOS transistor P3. Where this happens, third PMOS transistor P3 may be undesirably turned on.